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Senior Verification Engineer - S. Cal USA
The engineer will be responsible for verification of assigned sections of a next generation technology.
*Proficient in building constrained-random verification environments using advanced verification methodologies such as UVM, OVM, VMM or eRM *Skill in creating and analyzing coverage metrics including functional coverage, assertion coverage and code coverage metrics is essential*Experience with defining and creating SVA or PSL assertions, and using formal checking tools*The engineer must have a well developed ability to analyze specifications at the architecture and micro-architecture level to identify the test scenarios needed to achieve functional and performance goals...View full job description
From TechnoJobs
- 13 Feb 2012
*Proficient in building constrained-random verification environments using advanced verification methodologies such as UVM, OVM, VMM or eRM *Skill in creating and analyzing coverage metrics including functional coverage, assertion coverage and code coverage metrics is essential*Experience with defining and creating SVA or PSL assertions, and using formal checking tools*The engineer must have a well developed ability to analyze specifications at the architecture and micro-architecture level to identify the test scenarios needed to achieve functional and performance goals...View full job description
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